期刊文献+

基于可配置处理器的AES算法设计 被引量:1

AES Algorithm Based on Configuarable Processor
下载PDF
导出
摘要 研究高级加密标准AES算法的加密解密流程,分析算法的执行热点,并提出一种基于可配置处理器的优化方法,设计适合于AES算法的处理器配置,实现多条AES算法专用指令,并采用硬件查找表技术提高新处理器算法对热点的执行能力。实验结果证明,此方法大大减少了多个热点的执行周期数,提高了AES算法的执行效率。 This paper researches the encryption and decryption process of the advanced standard AES algorithm, and analyzes the execution hot points of the algorithm. The paper adopts a method based on configurable processor, designing a processor configuration to fit AES, implementing multiple special instructions for AES, and using hardware look-up table to improve the execution performance of the new processor algorithm on the hot points. Experimental result proves that the method decreases the number of execution cycles of the hot points and improves the execution efficiency of AES.
出处 《单片机与嵌入式系统应用》 2010年第3期52-54,共3页 Microcontrollers & Embedded Systems
关键词 加密 AES算法 可配置 Xtensa处理器 TIE语言 encryption AES algorithm configuarable Xtensa processor TIE language
  • 相关文献

参考文献5

二级参考文献19

  • 1Daemen J,Rijmen V.AES Proposal:Rijndael.http://www. Daemen.j@banksys
  • 2Specification for the ADVANCED ENCRYPTION STANDARD(AES)[S].FIPS DRAFT, 2001: http://csrc.nist.gov/pu blications/drafts/dfipsAES.doc
  • 3AV McCree,TPBarnwell.A mixed excitation LPC vocoder model for low bit rate speech coding.IEEE Transactions on Speech and Audio Processing,July 1995,3 (4):242~250
  • 4L M Supplee,R P Chon,J S Collura,et al.MELP:The new federal standard at 2400bps.in Proc.ICASSP,1997,2:1591~1594
  • 5R Martin,R V Cox.New speech enhancement techniques for low bit rate speech coding.in Proc.Speech Coding Workshop,1999:165~167
  • 6D P Kemp,J S Collura,T E Tremain.Multi-frame coding of LPC parameters at 600~800bps.Proc.IEEE Inter Conf.Acoustics,Speech and Signal Processing,1991,1:609~612
  • 7A V McCree,J C DeMartin.A 1.7 kb/s MELP coder with improved analysis and quantization.Proc.IEEE Inter.Conf.Acoustics,Speech and Signal Processing,1998:593~596
  • 8A McCree,K Truong,et al.A 2.4 kbits/s MELP coder candidate for the new U.S.federal standard.Proceedings of IEEE ICASSP,1996:200~203
  • 9R E Gonzalez.Xtensa:a configurable and extensible processor.Micro,IEEE,April 2000,20:60~70
  • 10G Ezer.Xtensa with user defined DSP coprocessor microarchitectures.International Conference on Computer Design,IEEE,Sept.2000:335~342

共引文献21

同被引文献4

引证文献1

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部