基于FPGA的高速AES实现

Implementation of AES-128 using FPGA

通过对高级数据加密标准进行分析,给出了一种基于全流水线的的实现方法.这种实现方法同时支持加密和解密,具有低实现代价、高吞吐量等特点.采用Xilinx公司的Virtex-4 XC4VLX 1000-12芯片进行实现,结果表明吞吐量可以达到39.93 Gbit/s,适合高性能的加密应用要求.

Advanced encryption standard（AES） was analyzed.A method based on full pipelined architecture of the AES was proposed,by which the process of encryption and decryption can be completed at the same time.The implemented results on Xilinx Virtex-4 XC4VLX 1000-12 device show that the proposed implementation can achieve a throughput of 39.93 Gbit/s,which indicates this architecture is suitable for high-performance application.