采用νMOS管的多值计数器设计

Design of multi-valued counter based on νMOS

通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。

Through the research on the characteristics of vMOS and the principles of multi-valued logic circuits, this paper presents a design scheme of multi-valued counter. Two-valued coding method and vMOS characteristics, including multiple-input signals threshold operation and the floating gate capacitance coupling effect, are integrated together to implement this proposed scheme. PSPICE simulation is selected to verify the proposed circuit. The simulation results indicate that this multi-valued counter can provide correct logic function, and has characters including simple structure, low power and easy in realization.