800Mbps准循环LDPC码译码器的FPGA实现

An 800Mbps Quasi-Cyclic LDPC Decoder Implementation with FPGA

本文提出了一种适用于准循环低密度校验码的低复杂度的高并行度译码器架构。通常准循环低密度校验码不适于设计有效的高并行度高吞吐量译码器。我们通过利用准循环低密度校验码的奇偶校验矩阵的结构特点,将其转化为块准循环结构,从而能够并行化处理译码算法的行与列操作。使用这个架构,我们在Xilinx Virtex-5LX330FPGA上实现了(8176,7154)有限几何LDPC码的译码器,在15次迭代的条件下其译码吞吐量达到800Mbps。

In this paper,we propose an efficient highly-parallel decoder architecture for quasi-cyclic （QC） low-density parity-check （LDPC） codes,which leads to reduction in hardware complexity.Generally,QC-LDPC codes cannot be used to design a efficient highly-parallel decoding architecture for high-throughput applications.The QC-LDPC code parity matrix structure is exploited to parallelize the row and column decoding operations.Using this architecture,we have implemented a decoder for a （8176,7154） Finite geometry-based QC-LDPC code on a Xilinx Virtex-5 LX330 FPGA,and achieved decoding throughput of 800 Mbps with 15 fixed iterations.