基于SystemC语言的伪随机序列发生器设计

A Pseudo Random Sequence Generator Design Based on the SystemC

提出了一种基于SystemC的伪随机序列发生器硬件设计,并使用Agility Compiler软件完成了仿真。仿真结果表明,该设计方法效率高,且灵活性强。

A hardware design which generates pseudo random sequence is proposed based on the SystemC, and simulated with Agility Compiler. The simulated result illustrates that this design is very efficient and flexible.