期刊文献+

缓解同时多线程结构中线程对关键资源的竞争 被引量:1

Easing the Competition for Key Resource among Threads in SMT
下载PDF
导出
摘要 同时多线程处理器同时执行来自不同线程的指令,兼顾了线程内和线程间的指令并行,使处理器的性能得以大幅提升。然而这种对资源的共享方式,可能带来对关键资源(包括重命名寄存器、指令队列等)的恶性竞争,从而出现"饿死"现象,甚至影响处理器的吞吐率。这主要是由于某些线程遇到长延迟指令,并长期占据关键资源,从而导致其他线程对资源的需求无法得到满足,同时这也降低了资源的利用率。降低竞争带来的负面影响,主要有3种方法:线程调度——在取指段,决定从哪些线程取指令;指令调度——决定哪些指令进入关键资源;关键资源划分——为每个线程分配独立的关键资源。主要对这些调度策略进行综述。 Simultaneous Multithreading Processors boost performance by executing instructions from different threads simultaneously, which explore both inter-thread and intra-thread parallelism. Sharing critical resources (including rename register file, instruction queue and so on) among different threads may also bring vicious competition,which may resultin starvation,even degrade the performance.This is mainly due to long delays encountered by some thread,and the threads take a lot of key resources for long time,while the demand of the other threads for key resources cannot be met.This may reduce the utilization of resources.There are three methods to reduce the negative impact of competition:thread scheduling decides which threads to fetch instructions from in the fetch stage;instruction scheduling determine which instructions to enter the key resource in the dispatch stage;Partitions of the key resources allocate the key resources among threads.These scheduling strategies were reviewed in the paper.
作者 印杰 江建慧
出处 《计算机科学》 CSCD 北大核心 2010年第3期256-261,共6页 Computer Science
基金 国家科技部"九七三"计划项目(2005CB321604)资助
关键词 同时多线程 线程调度 指令调度 资源划分 SMT, Thread scheduling, Instruction scheduling, Resources partitions
  • 相关文献

参考文献38

  • 1Marr D T, Binns F, Hill D L, et al. Hyper-Threading Technology Architecture and Microarchitecture [J]. Intel Technology Journal,2002,6(1) : 4-15.
  • 2Preston R P, et al. Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading[C]//Proc. of IEEE International Solid-State Circuits Conference. San Francisco, USA, February 2002 : 334-335.
  • 3Agarwal A, Lim B H, Kranz D, et al. APRIL: A Processor Architecture for Multiprocessing[C] //17^th Annual International Symposium on Computer Architecture. Seattle, WA, USA, June 1990:104-114.
  • 4Alverson R, Callahan D, Cummings D, et al. The Tera Computer System[C]//Proc. of the 4^th International Conference on Supercomputing. Amsterdam, June 1990 : 1-6.
  • 5Laudon J,Gupta A, Horowitz M. Interleaving:A Multithreading Technique Targeting Multiprocessors and Workstations[C]// Proc. of the 6^th International Conference on Architectural Support for Programming Languages and Operating Systems. San Jose, California, USA, October 1994 : 308-318.
  • 6Smith B J. Architecture and Applications of the HEP Multiprocessor Computer Systems [J]. Real Time Signal ProeessingⅣ, 1981,298:241-248.
  • 7Knijnenburg P M W, Ramirez A, Latorre F, et al. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures[C]//Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. Kohala Coast, Big Island, Hawaii ,January 2002:67-76.
  • 8Tullsen D M, Eggers S J, Levy H M. Simultaneous Multithrea - ding: Maximizing On-Chip Parallelism[C]//Proc. of 22^nd Annual International Symposium on Computer Architecture. Santa Marguerite Liguria, Italy, 1995 : 392-403.
  • 9Tullsen D M, Eggers S J, Levy H M, et al. Exploiting Choice: Instructions Fetch and Issue on an Implementable Simultaneous Multithreading Processor[C]//23^rd Annual International Symposium on Computer Architecture. Philadelphia, PA, USA, May 1996:191-202.
  • 10Evers M, Yeh T-Y. Understanding Branches and Designing Branch Predictors for High-Performance Microprocessors[J]. Proceedings of the IEEE,2001,89(11) :1610-1620.

二级参考文献48

  • 1杨华,崔刚,刘宏伟,杨孝宗.两级分配多可用重命名寄存器[J].计算机学报,2006,29(10):1729-1739. 被引量:2
  • 2D M Tullsen,S J Eggers,H M Levy,et al.Simultaneous multithreading:Maximizing on-chip parallelism[C].In:Proc of the 22nd Annual Int'l Symposium on Computer Architecture.Los Alamitos,CA:IEEE Computer Society Press,1995.392-403
  • 3D M Tullsen.Exploiting choice:Instruction fetch and issue on an implementable simultaneous multithreading processor[C].In:Proc of the 23nd Annual Int'l Symposium on Computer Architecture.Los Alamitos,CA:IEEE Computer Society Press,1996.191-202
  • 4Quality of service networking[OL].http://www.cisco.com/univercd/cc/td/doc/cisintwk/ito doc/qos.htm,2001
  • 5M P Wilson.Thread selection policies on a simultaneous multithreading processor[OL].http://www.tinker.ncsu.edu/ericro/ece721/student projects/mpwilson.pdf,1999
  • 6S Raasch,S Reinhardt.Applications of thread prioritization in SMT processors[C].In:Proc of Multithreaded Execution and Execution Workshop (MTEAC).Los Alamitos,CA:IEEE Computer Society Press,1999
  • 7F J Cazorla,P M W Knijnenburg,R Sakellariou,et al.Predictable performance in SMT processors[C].In:Proc of CF'04.Los Alamitos,CA:IEEE Computer Society Press,2004.433-443
  • 8He Liqiang,Liu Zhiyong.An effective instruction fetch policy for simultaneous multithreaded processors[C].In:Proc of the 7th HPCAsia.Los Alamitos,CA:IEEE Computer Society Press,2004.162-168
  • 9Ali EI-Moursy,H A David.Front-end policies for improved issue efficiency in SMT processors[C].In:Proc of the 9th Int'l Symposium on High-Performance Computer Architecture.Los Alamitos,CA:IEEE Computer Society Press,2003.31-40
  • 10P Michaud,A Seznec,S Jourdan.An exploration of instruction fetch requirement in out-of-order superscalar processors[C].International Journal of Parallel Programming,2001,29(1):35-58

共引文献8

同被引文献14

  • 1孙彩霞,张民选.DWarn+:一种改进的同时多线程处理器取指策略[J].小型微型计算机系统,2007,28(9):1720-1723. 被引量:3
  • 2Knijnenburg P M W,Ramirez A,Latorre F. Branch classification to control instruction fetch in simultaneous multithreaded architectures[A].Kauai:IEEE Computer Society,2002.67-76.
  • 3Raasch S E,Reinhardt S K. The impact of resource partitioning on SMT processors[A].New Orleans:IEEE Computer Society/ACM/IFIP,2003.15-25.
  • 4Joshua J Y,Ajay J,Resit S. Analyzing the processor bottlenecks in SPEC CPU 2000[A].Austin:SPEC,2006.
  • 5印杰.同时多线程处理器容错技术研究[D]上海:同济大学电子与信息工程学院,2011.
  • 6Cazorla F J,Ramirez A,Valero M. Dcache warn:an i-fetch policy to increase SMT efficiency[A].Santa Fe:IEEE Computer Society,2004.74-83.
  • 7Sharkey J J,Ponomarev D V. Efficient instruction schedulers for SMT processors[A].Austin:IEEE Computer Society,2006.288-298.
  • 8Wang H,Sangireddy R,Baldawa S. Optimizing instruction scheduling through combined in-order and O-O-O execution in SMT processors[J].{H}IEEE Transactions on Parallel and Distributed Systems,2009,(03):389.
  • 9Brekelbaum E,Rupley J,Wilkerson C. Hierarchical scheduling windows[A].Istanbul:IEEE Computer Society/ACM,2002.27-36.
  • 10Cristal A,Ortega D,Llosa J. Out-of-order commit processors[A].Madrid:IEEE Computer Society,2004.48-59.

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部