复分接中数字化定时处理的参数化验证法

Digital Timing Processing Verification in Multiplex Circuits Based on Parameter Estimation

在复分接系统中，如同步数字系列（SDH），定时处理占有重要地位。数字化定时处理技术应用于ASIC设计时，传统方法需要的仿真代价太大。作者指出了定时验证的特殊性，提出了定时处理电路验证的概念。同时利用参数化方法对定时处理进行验证，大大缩短了仿真时间。

In multiplex and demultiplex systems such as Synchronous Digital Hierarchy(SDH), timing processing is very important to system performance. Modern digital timing processing technology is widely used in ASIC design for such systems. However, the conventional verification and test methods are not suitable for timing processing circuits. The concept of digital timing processing verification is proposed in this paper and its characteristics are illustrated. The novel verification method based on parameter estimation is explored. It is shown to e very effective in simulation time reduction by experiments.