一种Turbo乘积码编译码器的设计与实现

Design and Implementation of a Turbo Product Code Encoder and Decoder

分析了Turbo乘积码的线性编码和基于Chase算法的软输入软输出迭代译码方法,讨论了硬件可实现的低延迟编码器、译码器应具有的结构特点,并采用此方法设计了1个长度为1024bit、码率66%的Turbo乘积码。该编码器工作时钟和输入数据速率相同,译码器则需要3倍于输入数据速率的时钟,译码器理论吞吐率可达60Mb/s。实测结果表明,其性能和仿真值相差不大于0.4dB。

This paper analyzes the method of designing Turbo product codes based on Chase algorithms, and describes the structure of encoder and decoder that can be implemented in hardware. With this method, a 1024bit, 66% rate Turbo product code is designed. The encoder＇s clock frequency is the same to its input, and the decoder＇s clock frequency is three times higherl than its input, of which the theoretic throughput 6an be up to 60 Mb/s. It＇s shown that the decoder＇s performance is within 0.4dB from the computer simulation.