32位无符号并行乘法器的设计与实现

Design and Implementation of a 32-Bit Unsigned Parallel Multiplier

在基4的Booth算法得到部分积的基础上,采用了优化后的4:2压缩器的Wallace树对部分积求和,最后用CPA得到最终的和。优化下的并行乘法器比传统的CSA阵列乘法器速度快,且延时小。用Verilog进行了功能描述,并用ISE9.2对其进行了综合。

Based on the traditional Booth 4 algorithm, we adopt the Wallace tree of a balanced 4：2 compressor to compute the sum of partial products and finally use CPA to get the final sum. It is shown that this scheme has a higher speed and a small delay than the traditional CSA array multiplier. The circuit is described using the Verilog HDL language and is synthesized by ISE9. 2.