基于Altera Stratix的LDPC编译码器的工程实现

A FPGA Implementation for LDPC En-Decoder Based on Altera Stratix

实现了一种相对高效的低密度校验码的编码方法,这种基于循环移位矩阵的准循环低密度校验码的设计方法既有较好的性能又有实际应用中可接受的编码复杂度。同时实现了一种高性能、低复杂度的软判决译码算法。这种译码算法较常用的硬判决译码算法性能出色,同时较一般的迭代译码算法的收敛速度快,并且可以部分并行译码,需要的存储量很小,能够大幅度降低低密度校验译码的硬件实现复杂度,具有很大的工程应用价值。

A high-performance design based on code matrix shift of LDPC is implementated, which has better error-correct capabilities and less encode complexity for FPGA implementation. Meanwhile, a soft-decision decoding algorithm is implemented, and this algorithm is of high performance, high-speed convergence and so on. This parallel decoding is used to implement the decoder, and the design the requires fairly low memory capacity and low hardware implantation complexity, and so is of great value for engineering application.