嵌入式存储器自修复电路的设计与仿真

Design and Simuiation of Embedded Memory Self-repaired Circuits

介绍了一种存储器自修复电路的仿真设计，其中内建自测试模块中的地址生成器采用LFSR设计，它面积开销相当小，从而大大降低了整个测试电路的硬件开销。而内建自修复模块采用基于一维冗余（冗余行块）结构的修复策略设计。通过16×32比特SRAM自修复电路设计实验验证了此方法的可行性。

Design and simulation of a memory self-repaired circuit is presented. The part of built-in self-test circuit is based on LFSR （ line- ar feedback shift registers） . The area overhead of address generator based on LFSR is very low, thus the whole hardware overhead of self-test cir- cuit is greatly reduced. The repair strategies design based on one-dimension redundant blocks is adopted in the part of built-in self-repaired cir- cuit. The experiment of a 16 × 32b SRAM self-repaired circuit verifies the feasibility of the technique.