摘要
采用CSMC 0.5μm40 V工艺和Spectrum仿真平台,设计一款应用于电压保护芯片的LDO(Low Dropout)低压差线性稳压电路。该电路选择PMOS结构的调整管,不需要增加额外的电荷泵电路来驱动;采用带隙基准电压源结构,在1 kHz频率下,电源电压抑制比(PSRR)为-67.32 dB,在1 MHz频率下为-33.71 dB;在误差放大器设计中引入频率补偿,改善了稳压器的线性调整率性能。仿真结果表明,常温下当输入电压从1.6 V变化到6.6 V时,输出电压稳定在1.258 V左右,温度系数为31.38 ppm,在100 kΩ负载下显示出良好的稳压性能。
Low dropout linear voltage stabilizer for voltage protection is presented. The circuit is designed in CSMC 0.5 μm 40 V technology and simulated by spectrum tool. Since PMOS adjustment transistor is selected, the additional charge pump driving circuit is not needed. The band - gap voltage reference structure is employed. The PSRR is - 67.32 dB at 1 kHz and -33.71 dB at 1 MHz. The frequency compensation network is used in the error amplifier design to improve the performance of linear adjustment ratio. The simulation results that the reference voltage is about 1. 258 V while the input voltage varies from 1.6 V to 6.6 V at the room temperature,the temperature coefficient is 31.38 ppm. The circuit shows good voltage stabilizer ability under 100 kΩ load.
出处
《现代电子技术》
2010年第6期16-18,28,共4页
Modern Electronics Technique
基金
湖北省教育厅重点科研资助项目(D20081002)
