基于神经网络混沌吸引子公钥加密算法的FPGA实现

FPGA Implement of Public-key Cryptography Based on Chaotic Attractors of Neural Networks

利用具有顺序和并行执行的特点的VHDL语言,设计并实现了基于神经网络混沌吸引子的公钥加密算法,在编解码器设计中采用专用的控制模块来控制加密和解密操作;同时,在RAM模块中自主设计了具有并行读写功能的子模块,以进一步提高算法的数据加密速度;整个系统在DE2实验平台中经过反复实验测试和试运行,结果表明该算法是可以硬件实现的,并且具有较高的数据加密速度,时钟频率可达50 MHz以上.

This paper presents an implement of public-key cryptography based on chaotic attractors of neural networks using VHDL language, as VHDL code can be concurrent or sequential specially. In detail, a special control module is designed to manipulate encryption or decryption in the encoder-decoder, and a new ram module is devised in which multicell can be read or written concurrently,the calculation speed accelerates obviously as a result. The whole design can run in DE2 stably,which clock frequency is above 50 MHz. The result shows that the public-key cryptography based on chaotic attractors of neural networking can he put into hardware and get a higher clock frequency.