FIR数字滤波器的FPGA实现研究

Research of FIR digital filter implementation with FPGA

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能,在Xilinx ISE10.1开发平台中,采用Verilog HDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构,并在ModelSim仿真验证平台中仿真了实现设计。结果表明,改进串行结构的实现消耗资源少但滤波速度慢,并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少。

In order to research different implementations of FIR digital filter with FPGA on their resource consuming as well as the speed performance,the improved serial structure,parallel structure and DA structure of FIR digital filter were respectively implemented with Verilog HDL on the Xilinx ISE10.1 development platform,and then simulated on the Modelsim simulation platform.It turns out that the implementation of improved serial structure consumes resource least but the filter speed is low,and the parallel structure has a fastest filter speed but consumes resources most.Whereas,the filter speed of DA structure only depends on the width of input data,so its filter speed is usually faster than improved serial structure but the consuming resource is less then parallel structure.