摘要
介绍一个适用于低中频架构的四阶连续时间正交带通ΣΔ调制器的设计,通过采用复数积分器代替传统的谐振器,优化了调制器的噪声整形性能。调制器采用开关电容反馈DAC来减少对时钟抖动的敏感度。电路设计采用smic0.13mixed-signalCMOS工艺,仿真结果表明,在12MHz采样频率下,调制器的信号噪声失真比可达到78dB,其信号带宽为200kHz,中心频率在200kHz。
The design of a fourth-order continuous-time quadrature band-pass ∑A modulator for low-IF architecture is introduced. The noise shaping performance of the modulator is optimized by using the complex integrator instead of the traditional resonator. The switched-capacitor feedback DAC is chosen in the modulator to reduce the sensitivity to clock jitter. The modulator is designed in stoic 0. 13 mixed-signal 1P6M COMS process. Simulation results indicate that the modulator achieves a SNDR of 78 dB over a 200 kHz passband centered at 200 kHz at the sampling rate of 12 MHz.
出处
《电子器件》
CAS
2010年第1期58-61,共4页
Chinese Journal of Electron Devices