期刊文献+

四阶连续时间正交带通ΣΔ调制器的设计 被引量:1

The Design of a Fourth-Order Continuous-Time Quadrature Band-Pass ΣΔ Modulator
下载PDF
导出
摘要 介绍一个适用于低中频架构的四阶连续时间正交带通ΣΔ调制器的设计,通过采用复数积分器代替传统的谐振器,优化了调制器的噪声整形性能。调制器采用开关电容反馈DAC来减少对时钟抖动的敏感度。电路设计采用smic0.13mixed-signalCMOS工艺,仿真结果表明,在12MHz采样频率下,调制器的信号噪声失真比可达到78dB,其信号带宽为200kHz,中心频率在200kHz。 The design of a fourth-order continuous-time quadrature band-pass ∑A modulator for low-IF architecture is introduced. The noise shaping performance of the modulator is optimized by using the complex integrator instead of the traditional resonator. The switched-capacitor feedback DAC is chosen in the modulator to reduce the sensitivity to clock jitter. The modulator is designed in stoic 0. 13 mixed-signal 1P6M COMS process. Simulation results indicate that the modulator achieves a SNDR of 78 dB over a 200 kHz passband centered at 200 kHz at the sampling rate of 12 MHz.
出处 《电子器件》 CAS 2010年第1期58-61,共4页 Chinese Journal of Electron Devices
关键词 ΣΔ调制器 复数积分器 时钟抖动 开关电容DAC ∑A modulator complex integrator clock jitter switched-capacitor DAC
  • 相关文献

参考文献12

  • 1Jouida N, Rebai C, Ghazel A, et al. Continuous-Time Complex Bandpass △∑ Modulator: Key Component for Highly Digitized Receiver[ C]//ICECS, Nice, France, 2006 : 10 - 13.
  • 2Gerfers F, et al. A1.5 V, 12 bit Power Efficient Continuous Time △∑ Third-order Modulator [ J ]. IEEE J. Solid-State Circuits, 2003, 38(8) : 1343 - 1352.
  • 3Henkel F, Langmann U, Hanke A, et al. A 1 MHz-bandwith second-order continuous-time Quadrature Bandpass Sigma - delta Modulator for Low-IF Radio Receivers [ J]. IEEE J. Solid-State Circuits, 2002, 37( 12): 1628- 1635.
  • 4Esfahani F, Basedan P, Ryter R, et al. A Fourth-order Continuoustime Complex Sigma delta ADC for Low-IF GSM and EDGE Receivers [ C ]//VLSI Symp. Tech. Dig. , Kyoto, Japan, 2003 : 75 - 78.
  • 5Arias J, Kiss P, Prodanov V, et al. A 32-mW 320-MHz Continuoustime Complex Delta - Sigma ADC for Multi-mode Wireless-LAN Receivers[J]. IEEE J. Solid-State Circuits, 2006, 41(2): 339 -351.
  • 6Schreier R, Abaskharoun N, Shibata H, et al. A 375 mW Quadrature bandpass 16 ADC with 90 dB DR and 8.5 MHz BW at 44 MHz [J]. IEEE J. Solid-State Circuits, 2006, 41(12) : 2632-2640.
  • 7Ortmanns M, Gerfers F. Continuous-time Sigma-deha A/D Conversion[ M]. NY: Springer, 2006.
  • 8Ortmanns M, Gerfers F, Manoli Y. A Continuous-time Sigma-delta Modulator with Reduced Sensitivity to Clock Jitter through SCR- Feedback[ J]. IEEE Trans. on Circuits and Systems Ⅰ, 2005, 52 (5): 875-884.
  • 9Norsworthy S R, Schreier R, Temes G C. Delta-sigma Data Converters: Theory, Design, and Simulation [ M ]. IEEE Press, 1996.
  • 10van Veldhoven R H M. A Triple-mode Continuous-Time △∑ Modulator with Switched-capacitor Feedback DAC for a GSM-EDGE/ CDMA200/UMTS Receiver [ J ]. IEEE J. Solid-State Circuits, 2003, 38(12): 2069-2076.

同被引文献8

  • 1黄进,皇甫红军,张兴,黄如.1.6 GHz 24位4阶Σ-Δ小数分频频率合成器[J].微电子学,2006,36(5):683-687. 被引量:2
  • 2Keliu Shu.Edgar SāNchez-Sinencio,CMOS PLL Synthesizer:Analysis and Design[M].American:Springer,2005.
  • 3George I Bourdopoulos.Delta Sigma Modulators:Modeling,Design and Applications[M].London:Imperial College Press,2006.
  • 4Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,et al.A ∑-ΔFractional N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications[J].IEEE Solid State Circuits,2009,44(8):2197-2198.
  • 5Butterfield D,Sun B.Prediction of Fractional-N Spurs for UHF PLL Frequency Synthesizers[J].IEEE,1999.
  • 6Dehghani R.A 2.5 GHz CMOS Fully Integrated Delta-Sigma Controlled Fractional-N Frequency Synthesizer[C] //Proc IEEEnt Conf VLSI Design,2004,163-167.
  • 7何素东,吴建辉,周越.ΣΔ调制器的设计方法[J].电子器件,2008,31(2):516-519. 被引量:3
  • 8张海清,李文宏,林蔚然,曾晓洋,章倩苓.用于调制频率合成器的5bit 4阶误差反馈ΔΣ调制器设计[J].Journal of Semiconductors,2003,24(11):1200-1205. 被引量:1

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部