10bit 20MS/s流水线模数转换器设计

A 10 bit 20 MS/s Pipelined A/D Converter

设计了一个20MHz采样率,10bit精度流水线模数转换器。采用新颖的栅压自举开关,使电路在输入信号频率很高时仍具有良好的动态性能;用MATLAB仿真增益增强型运算放大器在不同反馈因子下闭环零、极点特性,提出了使大信号建立时间最短的主运放、辅助运放单位增益带宽和相位裕度范围。采用SMIC0.35μm2P4M工艺流片验证,20MHz采样率,2.1MHz输入信号下,SFDR=73dBc,ENOB=9.18bit。

Design of a 10 bit, 20 MS/s pipelined ADC with a novel low constant-impedance switch is proposed, which used the bootstrap method to reduce the variation of switch ＂on＂ resistances; Analyzed the close-loop pole-zero position in gain-boosted amplifier at different feedback coefficient, the optimum bandwidth for the main cascode and boosting amplifier is found. With this method, slow settling components in the large signal response are eliminated, resulting in the shortest settling time. The proposed ADC is designed and fabricated in SMIC 0. 35 μm 2P4M process. At 20 MHz sampling rate and 2.1 MHz input signal, SFDR of 73 dBc, ENOB of 9.18 bit are obtained.