TD-LTE系统中咬尾卷积码译码器的FPGA实现

FPGA implementation of a tail-biting convolution decoder application on TD-LTE system

在LTE中,为了获得正确无误的数据传输,要采用差错控制编码技术。LTE中是采用Viterbi和Turbo加速器来实现前向纠错。咬尾卷积码保证格形起始和终止于某个相同的状态,它具有不要求传输任何额外比特的优点。本文提出一种在FPGA中实现的咬尾卷积码的Viterbi译码算法,并在Xilinx的XC3S500E芯片上实现了该算法,最后对该算法性能进行了分析。

In LTE system,the error control coding techniques was used for attaining accurate data transmitting.Viterbi and Turbo accelerators applied on LTE to achieve the FEC.Tail-biting convolution code trellis to ensure a start and terminate in the same state,it has does not require any additional bits transmitted advantages.This paper presented an FPGA implementation of Viterbi algorithm based on tail-biting convolution codes.This decoder was implemented in Xilinx＇s XC3S500E chip.Finally,the algorithm performance was analyzed.