基于FPGA软核的佩带式心电信号处理系统的设计

Design of Wearable ECG Processing Prototype Based on FPGA Soft Core

心电信号分析结果是评价生理状态的重要依据,但是心电信号幅度小,极易受到外界干扰,提取和处理过程不易在佩带式家庭健康监护设备上完成。本文提出了一种基于FPGA软核的佩带式低功耗实时心电信号预处理系统,利用Actel Fusion FPGA内嵌的80c51软核作为主控制器,采用DA和CSD优化算法减少FIR数字滤波器硬件占用量,从而不但有效地对心电信号进行实时处理,而且减少了系统的体积和耗电量。经测试,该系统可以很好地满足设计要求,并且该系统的设计方法适合用于开发各种便携式实时生理状态监护设备。

The analysis result of ECG is an important evaluation indication for physiological status. Due to the weak amplitude, ECG is easily interfered during acquisition. This paper focuses on the development of a wearable, low power ECG processing prototype capable of extensive real-time ECG processing. The distinguishing feature is that there, is a soft core CoreSOc51 embedded in a low-power flash-based FPGA as the main controller. Specially, the potential of Distributed Algorithm （DA） and Canonic Signed Digit （CSD） code has been demonstrated in FIR filter applications to minimize the amount of used hardware. After the testing and tryout, the prototype could meet the design requirements, and the methodologies developed in this case study can enable adaptations to a wide range of pervasive heahhcare applications.