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一种通用的低成本QC-LDPC码译码结构

Generic Architecture with Efficient Memory Arrangement for QC-LDPC Codes Decoding
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摘要 提出一种通用的QC-LDPC码译码器架构.该架构采用一种特殊的绑定结构和一个可配置的循环移位网络,实现了多码率变码长的LDPC译码,可以应用在多标准数字通信系统中.同时,该结构使存储单元的利用率提高了13倍.提出的可配置数据交换网络可以使存储单元和运算单元之间的连线规则化,降低了连线复杂度.基于该结构,本文实现了符合中国数字电视地面传输标准DTMB中LDPC译码器,在SMIC0.18um标准COMS工艺下,芯片面积约为8mm2;在时钟频率50MHz,迭代次数15次,8比特量化的条件下,吞吐率可达91Mbps. In this paper,a generic architecture for QC-LDPC codes decoding is proposed.The novel architecture can perform decoding of multi-standard LDPC codes with multiple rates and variable lengths by introducing a special binding schedule and a scalable shuffle network.The new memory arrangement improves usage efficiency of memories as many as 13 times.A salable data exchange network is proposed to regularize wire connections,which efficiently reduces the interconnection complexity.Based on SMIC 0.18um standard CMOS process,the LDPC decoder for Chinese DTMB standard has an estimation area of 8mm2 with 8-bit quantization,and a throughput of 91Mbps with a frequency of 50MHz and maximum iteration number of 15.
作者 申睿 邓运松 向波 陈赟 曾晓洋
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《小型微型计算机系统》 CSCD 北大核心 2010年第3期566-570,共5页 Journal of Chinese Computer Systems
基金 上海市科学技术委员会(77062001)资助
关键词 QC-LDPC码 多标准 绑定结构 循环移位网络 QC-LDPC codes multi-standard binding schedule shuffle network
分类号 TP331 [自动化与计算机技术—计算机系统结构]
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参考文献19

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二级参考文献18

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小型微型计算机系统
2010年 第3期

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