乘法器复用技术在滑窗FIR滤波处理中的运用

The Application of the Multiplier Reused Technique for Slip-Window FIR Filter Processing

随着超大规模集成电路的飞速发展,FPGA集成的硬件乘法器越来越多,内核时钟越来越快,使得FPGA在实时信号处理中得到广泛应用。介绍了FIR滤波运算的原理与硬件处理结构,通过乘法器的复用技术,解决了实现滑窗FIR滤波处理时,FPGA内部乘法器的高速运算与外部慢速数据率之间的矛盾。

With the fast development of the super scale IC, the hardware multipliers integrated in FPGA is more and the core clock is faster, which make FPGA applied widely in real-time signal processing.The operating principle and hardware processing structure of FIR is introduced.By using the multiplier reused technique, the contradiction between the inner high-speed operation and the outside slow data rate in the slip-window FIR processing with FPGA is solved.