基于亚阈值漏电流的数据Cache低功耗控制策略研究

Research on Low Power Controlling Policies for Data Cache Based on Reducing Subthreshold Leakage Current

随着工艺尺寸及处理器频率的提高,Cache的功耗已经成为处理器功耗的重要来源,数据Cache的亚阈值漏电流功耗在总功耗中的比重也在上升;提出一种通过降低未被访问的Cache line的亚阈值漏电流功耗来降低整个数据Cache功耗的控制策略;该策略对所有Cache line周期性地提供低电压,从而降低了SRAM单元的亚阈值漏电流;当某一行被访问时,提供正常的电压,直到下一次被周期性地控制提供低电压;仿真结果显示,此策略以较少的硬件代价和访问延迟显著地降低了数据Cache的亚阈值漏电流功耗。

As feature size shrinks and the frequency increases, on--chip caches represent a sizable fraction of the total power consump- tion of microprocessors. Additionally, subthreshold leakage current as a percentage of total power consumption is on the rise. This paper presents a controlling policy that reduces the total Cache power by reducing the subthreshold leakage power of the Cache lines that are not accessed . It provides lower voltage to all the Cache lines periodically to reduce the subthreshold leakage current in SRAM cells. Normal voltage will be supplied to a line when it is accessed until the next cyclic lowvoltage signal arrives. The simulation results show that it can reduce the subthreshold leakage power of the data Cache efficiently at the expense of a little additional hardware and a slight performance loss.