可定制Tcore处理器指令调度设计

Design of Instruction Scheduling Based on Customizable Tcore Processor

基于传输触发体系结构可定制Tcore处理器具有理想的性能/价格比.但由于大量数据传输细节在体系结构一级可见导致了过低的编译效率.为此,提出了一种基于MACHSUIF中间格式的可重定目标编译器架构,将表调度与关键路径算法相结合以实现高效指令调度,从而大幅度提高编译质量.此外,通过基于操作的调度方法解决指令调度过程中功能单元的死锁问题.通过在4个DSP应用上进行测试,指令级并行度比传统的MoveFramework提高40%左右.

Customizable Tcore processor based on transport triggered architecture owns perfect tradeoff between performance and cost. But the feature of abundant data-transport details visible on the architecture level leads to low compilation efficiency. A retargetable compiler framework based on MACHSUIF intermediate format was presented, in which list scheduling and critical path algorithm were implemented to achieve highly efficient instruction schedul- ing so as to greatly improve the quality of compilation. Furthermore, the dead lock of function units was resolved thanks to scheduling based on operations. Compared with traditional MoveFramework, the instruction level parallelism was increased by about 40%, through tests on the four DSP applications.