纳米CMOS工艺下互连测试结构的设计与实现

Interconnect Test Structures Design and Realized in Nano CMOS Technology

集成电路制造技术进入纳米时代后,互连线制造过程中出现的半导体材料和工艺物理特性变异已不是仅靠晶圆厂或掩模厂采用的分辨率增强技术所能矫正。结合目前后段制程的工艺特点,设计了平行板电容、层跃平行板电容、叉指型电容、叉指型通孔链电阻等提取标准互连线性能参数的无源测试结构套件,并采用高阶Perl语言将其自动实现,极大地提高了测试结构设计和实现的效率。在此基础上,为建立可制造性设计的物理设计规则和进一步研发纳米工艺中互连线特有的各种新物理现象奠定了基础。

As manufacturing technology of integrate circuit into the nanometer era, the variations of semiconductor materials and processes physical properties during interconnect manufacturing can＇t be corrected only by previous resolution enhancement techniques offab or mask shop. Designed Parallel Plate, Layer-skipping Parallel Plate, Comb Meander, Comb Meander for via Resistance inactive test structure kits to extract Standard Interconnect Performance Parameters SIPPs, and automatically realized them with High-level Perl language. Greatly improved the efficiency of test structure＇s design and realized. Lay the foundations for formulation of DFM physical design rules and further research interconnection statistical models under nano technology with more unique physical phenomena.