RFID系统数据传输中CRC算法的分析与实现

Analysis and Implementation of CRC in RFID System

分析了基于ISO/IEC 18000-6协议的超高频(UHF)RFID系统数据传输中循环冗余校验(CRC)算法的原理和特点,在经典LFSR电路的基础上,采用按字节并行计算CRC校验码的方法,以CRC-CCITT生成多项式为例,用Verilog HDL语言设计实现了8位并行CRC-16电路.在Quartus Ⅱ8.0综合开发环境下进行时序仿真,并在FPGA芯片EP1C6Q240I7上测试验证,结果表明:所设计的电路在一个时钟周期内处理8位数据,符合协议规定,满足超高频RFID系统的通信速率要求.

This paper analyzes the principle and characteristic of CRC calculations in UHF RFID system data communications based on the ISO/IEC 18000-6 standard.Using a byte-wise method for parallel computing CRC and the Verilog HDL language,and taking CRC-CCITT generator polynomial for example,we designed a byte-oriented parallel CRC-16 circuit based on the classical LFSR circuit.Timing simulation in Quartus II 8.0 integrated development environment,and verifying it in the FPGA chip EP1C6Q240I7,the results show that this circuit we designed can processing 8 bit data per clock cycle.It is in agreement with the ISO/IEC 18000-6 standard and meet the requirements of communication rate in UHF RFID systems.