期刊文献+

利用RapidIO技术搭建的可重构信号处理平台 被引量:2

An implementation of reconfigurable signal processing system using RapidIO technology
下载PDF
导出
摘要 军事领域常选择ADI公司的TS201芯片用于信号处理平台,但由于其采用基于电路交换的LINK口进行连接,难以实现军方对电子系统设计提出的可重构性的需求。FPGA可以用来实现接口转换功能,如果利用FPGA将基于电路交换的LINK口转换成基于包交换的其他形式的接口,就能在不改变硬件连接的基础上,实现DSP系统的重构。本文介绍了一种基于串行RapidIO技术的可重构的信号处理平台,并对其中核心的FPGA的逻辑设计进行了讨论。 The DSP chip-TS201 from Analog Devices, Inc. uses link port, which is based on circuit switching ,to communicate. Such kind of interface makes it hard for the reconfiguration of an electronic system. FPGAs are usually used to realize an interface converter in electronic systems. If we use FPGA to convert the circuit-switching based interface to some other interface which is based on packet switching, we can realize the reeonfiguration of a system. In this paper, a reeonfignrable signal processing system using serial RapidlO technology is introduced, and the implementation of the crucial FPGA design is discussed.
出处 《电子技术应用》 北大核心 2010年第4期36-39,共4页 Application of Electronic Technique
关键词 串行RapidlO LINK口 可重构 信号处理机 DSP网络拓扑 serial RapidlO LINK port reeonfigurable signal processing system DSP network topology
  • 相关文献

参考文献5

  • 1FULLER S.RapidIO:The embedded system interconnect. Wiley, ISBN : 978-0-470-09291-0, US., 2005.
  • 2RapidIO Trade Association.RapidIO interconnect Specification Rev. 2.0. www. rapidio, org, 2008.
  • 3BOUVIER D,RapidIO:The interconnect architecture for high performance embedded systems.www.rapidio.org,2009.
  • 4Altera Corparation.RapidIO megacore function user guide. www. ahera.com.2008.
  • 5Altera Corparation. Avalon interface specification, www. altera.com.2008.

同被引文献9

  • 1Analog Devices Inc. TigerSHARC DSP hardware specification 1.1[Z]. 2004.
  • 2Altera Corparation. Quartus II Handbook Version 8.1 [ Z ]. 2008.
  • 3Ahera Corparation. Analog devices link-port reference design [EB/OL]. http://www, altera, com/literature/anfan 332. pdf,2005.
  • 4Ahera Corparation. AN433: constraining and analysing source-synchronous interfaces [ EB/OL]. www. altera, corn/ literature/air/an 433. pdf,2007.
  • 5FULLER S. RapidIO:The Embedded System Interconnect[M].USA:Wiley,2005.
  • 6RapidIO Trade Association. RapidIO interconnect Specification Rev.2.0[EB/OL].www.rapidio.org,2008.
  • 7岑凡.开放式体系结构的数字信号处理平台的研制[M]北京:中国科学院声学所,2009.
  • 8KAMAL R. Embedded Systems:Architecture,Programming and Design[M].India:Tata McGraw-Hill Education,2009.
  • 9朱含,岑凡,邢韬,何国建.基于FPGA实现DSP与RapidIO网络互联[J].微计算机信息,2009(26):129-130. 被引量:5

引证文献2

二级引证文献5

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部