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Low power CMOS preamplifier for neural recording applications 被引量:1

Low power CMOS preamplifier for neural recording applications
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摘要 A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extra- cellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process. A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extra- cellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第4期62-67,共6页 半导体学报(英文版)
基金 supported by the National Natural Science Foundation of China(Nos.60776024,60877035,60976026,90820002) the National High Technology Research and Development Program of China(Nos.2007AA04Z329,2007AA04Z254).
关键词 neural signal amplifier low noise low power subthreshold circuit design neural signal amplifier low noise low power subthreshold circuit design
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  • 1Hochberg L, Serruya M, Donoghue J, et al. Neural ensemble control of prosthetic devices by a human with tetraplegia. Nature, 2006, 442:164.
  • 2Nicolelis M. Brain-machine interface: past, present and future. Trends in Neurosciences, 2006, 29:536.
  • 3Bai Q, Wise K, Anderson R. A high-yield micro-assembly structure for three-dimensional electrode arrays. IEEE Trans Biomedical Eng, 2000, 47:281.
  • 4Nordhausen C, Maynard E, Normann R. Single unit recording capabilities of a 100-microelectrode array. Brain Review, 1996, 726:129.
  • 5Jochum T, Denison T, Wolf P. Integrated circuit amplifiers for multi-electrode intracortical recording. Journal of Neural Engineering, 2009, 6:1.
  • 6Harrison R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits, 2003, 38:958.
  • 7Najafi K, Wise K. An implantable multielectrode array with onchip signal processing. IEEE J Solid-State Circuits, 1986, 21: 1035.
  • 8Olsson R, Wise K. A three-dimensional neural recording microsystem with implantable data compression circuitry. IEEE J Solid-State Circuits, 2005, 40:2796.
  • 9Aziz J, Genov R, Derchansky M, et al. 256-channel neural recording microsystem with on-chip 3D electrodes. IEEE International Solid-State Circuits Conference, 2007:160.
  • 10Harrison R, Greger B, Solzbacher F. A low-power integrated circuit for a wireless 100-electrode neural recording system. IEEE J Solid-State Circuits, 2007, 42:123.

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