摘要
提出了一种基于流水线CORDIC的算法实现QAM调制,可有效节省硬件资源,提高运算速度。用Verilog HDL对本设计进行了编程和功能仿真,仿真结果表明,本设计具有一定的实用性。
This paper puts forward a pipelined architecture for implementation of QAM on FPGA based on CORDIC algorithm, which can save considerable hardware resources and improve the speed performance. And programs this design with Verilog HDL and carries out functional simulation. The results show that this design is valuable and feasible in practice.
出处
《微型机与应用》
2010年第7期52-54,57,共4页
Microcomputer & Its Applications