摘要
介绍了RS(255,223)码及其译码原理,基于修正欧几里德(Modified Euclidean,ME)算法提出了一种并行流水结构的硬件译码方案。按照自顶向下的设计流程划分模块,详细论述了各个子模块的设计过程,并给出了该结构的FPGA实现。相比现有的一些结构,该结构以较小的硬件资源代价,在相同时钟下数据吞吐率提高8倍,且大大降低了译码延迟。
The RS（255,223）decoder and its decoding principle are introduced.Based on Modified Euclidean（ME）algorithm,a hardware decoding solution using parallel pipeline architecture is proposed.Blocks are partitioned according to top-down design flow,and the design procedure of each block is discussed.The FPGA implementation is also given.Compared to other decoders,it has 8 times more throughput and lower decoding delay,taking only three times more hardware source under the same clock.
出处
《单片机与嵌入式系统应用》
2010年第4期17-20,共4页
Microcontrollers & Embedded Systems
