门时滞故障的可测性分析

Gate-Delay-Fault Testability Analysis

测试问题日益成为VLSI发展中的瓶颈问题,为了减少测试的困难,人们普遍接受的途径是在设计过程中就考虑电路的可测性,即采用可测性设计(DesLgn fo:Testab;lity)方法以减低测试成本。在可测性设计过程中可测性分析是极其重要的一环,所谓可测性是一种定量的测度,表示系统测试难易或测试性价比合理的程度。通过可测性分析人们可以找出电路中较难测试的区域,以便修改设计。

Recently, there has been interest in the design of testable combinational logical circuit under delay fault model, so it is necessary to discuss testability measure for delay fault. According to the feature of the testing for gate delay faults, we define the testability measures of the gate delay faults, it consists of the controllability and the observability of the gate delay faults in the rising (falling) transition. The computation of these two measures is based on the PREDICT algorithm[1] and the method of the paper[2], so it is practical and effective.