一种改进的适用于Sigma-Delta ADC的数字抽取滤波器

An Improved Digital Decimation Filter for Sigma-Delta ADC

数字滤波器在sigma-delta ADC芯片中占据了大部分芯片面积,该文提出了一种数字滤波器结构,这种结构滤波器采用一个控制单元和一个加法器取代了Hogenauer结构滤波器中差分器的多个加法器,从而减小数字电路的面积。一个采用这种结构的4阶的数字滤波器在CYCLONEⅡFPGA芯片中被实现,耗费的硬件资源比Hogenauer结构的滤波器减少近29%。

Usually in a sigma-delta ADC,the digital filter takes most of the chip area. In this paper,a novel digital filer topology is proposed,in which the differentiator is constructed with a control unit and an adder instead of the multiple of adders in the Hogenauer structure filter,so that the digital circuit area should be reduced. A fourth order digital filter employing such topology is implemented in a Cyclone-Ⅱ FPGA,and costs chip resources 29 percent less than in a Hogenauer structure.