期刊文献+

基于改进型(14,8)循环码的SRAM型存储器多位翻转容错技术研究 被引量:5

Study of the Fault Tolerant Technology Based on (14,8) CRC Code for SRAM's SWMU
下载PDF
导出
摘要 SRAM型存储器空间应用通常采取纠一检二(SEC-DED)的方法,克服空间单粒子翻转(SEU)对其产生的影响。随着SRAM型存储器工艺尺寸的减小、核心电压的降低,空间高能粒子容易引起存储器单个基本字多位翻转(SWMU),导致SEC-DED防护方法失效。在研究辐射效应引起的SRAM型存储器多位翻转模式特点的基础上,提出一种基于改进型(14,8)循环码的系统级纠正一位随机错和两位、三位突发错同时检测随机两位错(SEC-DED-TAEC)的系统级容错方法。基于该方法的存储器系统容错设计具有实现简单、实时性高的特点,已成功应用于某型号空间自寻的信息处理系统。仿真试验及实际应用表明,该方法可以有效防护SRAM型存储器件SWMU错误,有效提高了空间信息处理系统可靠性,可以为其它空间电子系统设计提供参考。 In space electronic system,the contents of SRAM are commonly protected by SEC-DED scheme. With the reduction of the feature size and the core power supply,the highly charged particles probably induce SWMU,leading to the failure of traditional SEC-DED scheme. Based on the physical signature for the SWMU of SRAM device,a modified (14,8) systematic SEC-DED-TAEC code is proposed. The design based on this code can be easily implemented and has been applied in a space-borne integrated processor platform. The real-time performance of the proposed method and the high reliability of the space-borne integrated processor have been demonstrated by simulation and the application results. It can provide important reference for other space information processing systems.
出处 《宇航学报》 EI CAS CSCD 北大核心 2010年第3期803-810,共8页 Journal of Astronautics
基金 国家"863"重大专项(2008AA8050701)
关键词 静态存储器 容错 单字节多位翻转 突发错误 可靠性 SRAM Fault tolerant SWMU Burst error Reliability
  • 相关文献

参考文献15

  • 1Underwood C I,Oldfield M K.Observations on the reliability of COTS-Device-Based solid state data recorders operating in Low-Earth orbit[J].IEEE Trans Nucl Sci,2000,NS-47:647-653.
  • 2Craig Hafer,Jonathan Mabra,Duane Slocum,et al.Next generation radiation-hardened SRAM for space applications[C].IEEEAC Dec,2005.
  • 3Maiz J,Hareland S,Zhang K,Armstrong P.Characterization of multi-bit soft error events in advanced SRAMs[J].IEDM Tech.Dig,Dec.2003:519-522.
  • 4Daniele Radaelli,Helmut Puchner,Skip Wong and Sabbas Daniel.Investigation of multi-bit upsets in a 150 nm technology SRAM device[J],IEEE Trans Nucl Sci,2005,52(6):2433-2437.
  • 5Tipton A D,Pellish J A,Reed R A,Schrimpf R D,Weller R A,Mendenhall M H,Sierawski B,Sutton A K,Diestelhorst R M,Espinel G,Cressler J D,Vizkelethy G.Multiple bit upset in 130 nm CMOS technology[J].IEEE Trans.Nucl.Sci.,2006,53(6):3259-3264.
  • 6Gill B,Nicolaidis M,Papachristou C,Wolff F,Garverick S.An efficient BICS design for SEUs detection and correction in semiconductor memories[C].Design Automation and Test Conference in Europe (DATE-05),2005.
  • 7Balkaran Gill,Michael Nicolaidis,Chris Papachristou.Radiation Induced Single-word multiple-bit upsets correction in SRAM[C].Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS'05),2005.
  • 8Shu Lin,Daniel J.Costello Jr.Error Control Coding Second Edition[M].ISBN 0-13-042672-5,2004.
  • 9Chen C L.Symbol error correcting codes for memory applications[C].Proc.of Fault Tolerant Computing Systems,1996:200-207.
  • 10赵建超,于伦正.空间粒子辐射引起存储单元多位比特纠错方案[J].微机发展,2005,15(12):154-156. 被引量:1

二级参考文献7

  • 1Koga R,IEEE Trans Nucl Sci,1993年,40卷,1491页
  • 2Koga R,IEEE Trans Nucl Sci,1991年,38卷,1498页
  • 3Integrated Device Technology Inc. Protecting Your Data With The IDT49C465 32 - BIT Flow - thruEDCTM UNIT[ Z].2002.1 - 73.
  • 4Vampola A L, Lauriente M,Wilkinson D C, et al. Signal event upsets correlated with environment[J ]. IEEE Trans on Nucl Sci, 1994,41 (6) :2383 - 2388.
  • 5蒋洵 熊剑平 尤政.利用FPGA实现模式可变的卫星数据存储器纠错系统[J].电子应用技术,2001,(7):107-112.
  • 6马振华.现代应用数学手册·离散数学卷[M].北京:清华大学出版社,2001.257-274.
  • 7Zoutendyk J A,Schwartz H R, Smith L S. Characterization of Multiple- bit Errors from Single- lonTrack sinintegrated circuits[J]. IEEE Trans on Nud Sci, 1989,36(6) :2267 - 2374.

共引文献3

同被引文献68

  • 1冯彦君,华更新,刘淑芬.航天电子抗辐射研究综述[J].宇航学报,2007,28(5):1071-1080. 被引量:69
  • 2贺朝会,耿斌,李永宏,惠卫东.大规模集成电路单粒子闭锁辐射效应测试系统[J].核电子学与探测技术,2005,25(6):724-728. 被引量:11
  • 3向春清,谭培勇.一种卫星存储器纠错检错系统设计[J].淮阴工学院学报,2007,16(3):40-43. 被引量:3
  • 4Rajsuman R. Design and test of large embedded memories: an overview[ J ] IEEE Design and Test of Computers, 2001, 18 (3) : 16 -27.
  • 5Leray J L. Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems [ J ] Microelectronics Reliability, 2007, 47(9 - 11 ) :1827 - 1835.
  • 6Baumann R C. Radiation-induced soft errors in advanced semiconductor technologies [ J ]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3) : 305 -316.
  • 7Cardarilli G C, Leandri A, Marinucci P, et al. Design of a fault tolerant solid state mass memory [ J ]. IEEE Transactions on Reliatility, 2003, 52(4): 476-491.
  • 8Kirn J, Hardavellas N, Mai K, et al. Multi-bit error tolerant caches using two-dimensional error coding [ C ]. 40th Annual IEEE/ACM International Symposium on Microarchitecture, Chicago, USA, December 197 - 209, 2007.
  • 9Naseer R, Draper J. Parallel double error correcting code design to mitigate multi-bi! upsets in SRAMs[ CI. 34th European Solid- State Circuits Conference, Edinburgh, U. K. , September 222 - 225, 2008.
  • 10Neuberger G, Kastensmidt D L. Multiple bit upset tolerant SRAM memory [ J ]. ACM Transactions Design Automation Electronic Systems, 2003, 8(4) : 577 -590.

引证文献5

二级引证文献18

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部