开放式电阻抗成像中数字相敏检波器设计

Digital Phase-Sensitive Detector Design for Open-Electrical Impedance Tomography

开放式电阻抗成像技术对测量系统的精度要求很高,为此研制了基于FPGA的数字相敏检波器(DPSD)以用于电阻抗成像的数据测量。通过分析DPSD的信号采集与计算原理,给出了关键参数的计算,基于DDS技术的ADC时钟设计方法。同时设计了高速多通道ADC转换电路,低抖动性能的ADC时钟电路、FPGA实现实时数字相敏检波的计算方法,提高了系统的信噪比。经实验测试表明,在1KHz^1MHz正弦信号注入频率的条件下,系统的信噪比最高可达104dB,精度高,稳定度好。

Electrical Impedance Tomography （EIT） system demands high precision of measurement result, thus the FPGA-based Digital Phase-Sensitive Detector （DPSD） was developed for data collection of EIT. By analyzing the principle of DPSD signal acquisition and calculation, the system＇s Signal-to-Noise-Ratio was obtained, the calculation of the key parameters and the method of designing ADC clock based on DDS technology were given. The high-speed multi-channel ADC conversion circuit, low-jitter performance of the ADC clock circuit and real-time DPSD method of calculation by FPGA realization were designed, to improve system SNR. Experiment shows that the system has high precision and good stability with SNR up to 104dB when injecting current frequency varies from 1kHz to 1MHz.