重掺杂衬底CMOS电路的衬底噪声耦合模型

The Substrate Crosstalk Resistance Mesh Model for heavily doped substrate CMOS circuit

本文为研究重掺杂衬底CMOS工艺中的耦合噪声建立了一个准确的衬底模型。该模型需要几个拟合的参数,可以从器件模拟或是实际测量中得到。基于CMOS0.35um工艺,设计了一个带隙电压源电路,加入衬底电阻网格模型,对比了SPICE和实际测试的结果,验证了模型准确性,并探讨了衬底噪声的特性。

An accurate substrate crosstalk coupling model for heavily doped CMOS processes is presented. The model requires several parameters which can be extracted from a few of simple device simulations or measurements. The model is validated by the comparison of the test and simulation result form a bandgap circuit. The substrate mesh model is add into the circuit in the simulation. We also study the characteristics of substrate crosstalk.