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一种缩短共享存储访问时延的优化仲裁技术

Optimization arbiter technique of reducing latency in sharing memory access SOC
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摘要 提出一种提高访问性能的优先级仲裁策略,按照不同类型的内存访问优先级进行分层仲裁,并通过隐藏bank预充电时延提高了内存访问效率。本方法应用于网络处理器(XD-NP)的可配置SDRAM控制器的设计中,并在FPGA平台上进行了验证,结果表明,采用延时隐藏策略的SDRAM控制器性能提升最大可达40%以上,改善明显。 This paper presented an optimization stratified arbitration policy to enhance the performance of SOC,accomplished arbitration according to different kinds of priority level,and improved memory access efficiency by using time-hiding techniques.This method was applied to configurable SDRAM in network processor and FPGA platform.The validation results show the speed and performance of memory access can be improved significantly up to 40%.
出处 《计算机应用研究》 CSCD 北大核心 2010年第4期1391-1393,1399,共4页 Application Research of Computers
基金 国家自然科学基金资助项目(60506020) 陕西省科技厅自然科学基础研究计(SJ08-ZT13)
关键词 多处理器片上系统 优先级仲裁 内存访问 时延隐藏 multi-processor SOC priority arbitration memory access time-hiding
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参考文献4

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