摘要
对功率集成电路中耐压为60V,电流容量为2.5A的VDMOS进行了设计和仿真。在理论计算的基础上,分析了外延参数和单胞尺寸结构的设计优化方法。通过ISETCAD器件仿真软件,得出相关数据和终端结构,进而借助L-edit完成最终版图结构。
In this paper, voltage for 60 V, current capacity of 2. 5 A for the VDMOS is designed and simulated, which is used in power IC. Based. on theoretical calculation, the epitaxial parameters and the optimization method of the structure design for cell size is analyzed. Relevant data and terminal structure are obtained by ISE TCAD device simulation software, and the layout structure is completed by L-edit.
出处
《电子科技》
2010年第4期33-35,41,共4页
Electronic Science and Technology
