可实现快速锁定的FPGA片内延时锁相环设计

A Fast-lock Delay-locked Loop for FPGA

延时锁相环(DLL)是一种基于数字电路实现的时钟管理技术。DLL可用以消除时钟偏斜,对输入时钟进行分频、倍频、移相等操作。文中介绍了FPGA芯片内DLL的结构和设计方案,在其基础上提出可实现快速锁定的延时锁相环OSDLL设计。在SMIC0.25μm工艺下,设计完成OSDLL测试芯片,其工作频率在20～200MHz,锁定时间相比传统架构有大幅降低。

The Delay-Locked Loop（DLL） is a popular clock management technique, which is mainly designed with digital circuits. The DLL can be adopted to solve clock signal skew, and to provide multiple phases of the source clock. The DLL can also act as a clock doubler or divider of the user source clock. The structure and design specifi- cation of a DLL on FPGA chip is presented. Based on the formal version DLL, a new fast-lock delay-locked loop, OSDLL, is designed and fabricated by the SMIC 0. 25μm CMOS process. It can operate at an input frequency ranging from 20 MHz to 200 MHz. Compared with conventional DLIs, OSDLL requires less time to lock the clock.