基于FPGA的液晶显示接口设计

Design of interface for LCM based on FPGA

为了解决CPU处理速度快,而液晶显示模块处理速度慢的矛盾,提高系统的运行的速度。利用FPGA以及异步FIFO的IP核实现液晶显示接口,在CPU和液晶模块之间建立一个FIFO缓冲区。同时根据液晶模块控制的流程设计了一个有限状态机,对液晶的数据命令信号进行控制,满足液晶模块读写的时序,实现了液晶模块控制命令以及显示数据的正确写入。测试结果表明,整个接口设计实现方式简单,可靠。

For solving the conflict between high-speed CPU and low-speed LCM and increasing running-speed of system, based on FPGA and IP core of asynchroronous FIFO, it set up an interface which involves a FIFO buffer between CPU and LCM. Based on the flow of LCM, it designs a finite state machine, which achieves control of data/command port, satisfies timing sequence of LCM and guarantees write-in of controlling command and data correctly. Through test, it has been found that the design is simple and it has high reliability.