摘要
TCAM是高性能路由器中查找性能强大的硬件查找结构,但是其价格昂贵且功耗大。为了解决这个问题,本文提出了一种实现方案,从而优化了TCAM电路结构且提高了性能。用Verilog HDL语言进行描述,采用Altera公司的FPGA开发权,基于CycloneⅢ单元库进行FPGA验证,此方案其时钟频率为100MHz,功耗降低50%。
TCAM is a most powerful hardware lookup table,however,it is of big cost and high power consumption.In order to solve the problems,this paper presents an implementation for optimizing the circuit structure and enhancing the performance on TCAM.This scheme is described in Verilog HDL and implemented by the Cyclone Ⅲ based FPGA of Altera Corporation.The clock frequency of this scheme is 100Hz,and power consumption reduces by 50%.
出处
《西安邮电学院学报》
2010年第1期110-114,共5页
Journal of Xi'an Institute of Posts and Telecommunications
基金
国家自然科学基金资助(60976020)
陕西省教育厅项目资助(08JK429)
