一种用于14位1.28MS/sΣΔADC的数字抽取滤波器设计

Decimation filter design for 14-bit 1.28MS/s sigma-delta ADC

设计了一种数字抽取滤波器,此滤波器由多级级联结构组成,对sigma-delta调制器的输出信号进行滤波和64倍的降采样,具有较小的电路面积和较低的功耗.采用TSMC 0.18μm CMOS工艺实现,工作电压1.8 V,流片测试结果表明:sigma-delta调制器输出信号经过数字抽取滤波器后,信噪失真比(SNDR)达到了93.9 dB,满足设计要求.所提出的数字抽取滤波器-6 dB带宽为640 kHz,抽取后的采样频率为1.28 MHz,功耗为33 mW,所占面积约为0.4 mm×1.7 mm.

A decimation filter for a 4th-order single-bit single-loop oversampling sigma-delta modulator is designed.Consisting of multi stages,the decimation filter is used to filter the noise in the output signal of the modulator and has a decimation factor of 64.It has a small circuit area and low power dissipation.The filter has been fabricated by the TSMC 0.18μm CMOS process and operates at a voltage of 1.8V.Experimental results show that the output signal of the decimation filter has an SNDR（Signal-to-Noise-and-Distortion-Ratio） of 93.9dB which meets the requirement of the system design.The presented filter has a-6dB pass-band of 640kHz,a power dissipation of 33mW and occupies a die area of about 0.4mm×1.7mm.