自适应时钟技术在芯片设计与验证中的应用

Application of Adaptive Clocking Technology in Chip Design and Verification

随着嵌入式处理器和DSP性能的迅速提升,传统的JTAG接口设计已经无法满足高速仿真器与高速目标芯片之间的时序要求。在此,提出一种双向同步自适应时钟技术,它不仅能够在仿真器与目标芯片间实现稳定可靠的信号传输,还可以根据目标芯片的时钟频率变化,动态地调整JTAG信号的传输速度,使整个调试系统始终工作在最佳状态。此外,利用该技术还成功地解决了软/硬件协同验证中真实系统与硬件模拟器之间信号传输的难题。

With the development of embedded processor and DSP′s performance, sincethe traditional JTAG interface can not meet the requirement of time sequence between the high-speed emulator and target chip, an adaptive clocking technology is proposed, which can realize the stable and reliable transmission of signals between emulator and target chip, can dynamically adjust the transmission speed of JTAG signal according to the frequency variation of the target chip′s clock. This new JTAG interface also can resolve the problem ofthe signal transfer between the real digital system and the hardware simulator in software/hardware co-verification.