基于新型双模分频器的低功耗多模分频器

A Low-Power Multi-Modulus Divider Based on New Dual-Modulus Divider

提出了一种基于新型源耦合逻辑或门的双模分频器和一种基于双D触发器的双模分频器。与传统的基于与门逻辑的双模分频器相比,基于新型源耦合逻辑的双模分频器减少了一级堆叠管,增加了采样开关管的过驱动电压,提高了工作速度。基于双D触发器的双模分频器比传统的基于4个D触发器的双模分频器节省近一半的晶体管,减小了芯片面积,降低了多模分频器的功耗。基于上述两种新型双模分频器架构,并引入分频比扩展技术,在0.18μm CMOS工艺下,实现了一种宽工作范围高速低功耗的多模分频器,分频范围为4～8192,工作频率范围0.8～2.7GHz,消耗电流1.25 mA。

New dual-modulus dividers （DMD） based on new source-couple logic （SCL） ＂OR＂ gate and on dual D- type flip-flop were proposed. Compared with traditional DMD based on SCL ＂AND＂ gate, the novel SCL-based DMD eliminates a stage of stacking transistors to increase overdrive voltage of switching transistors and speed. A DMD based on dual D-type flip-flop was also introduced, in which number of transistors was reduced by about half, compared with quad D-type flip-flop architecture, and it also occupies smaller chip area and consumes less power. Based on the two DMDs and using division ratio extension technique, a high speed and low power multi-modulus divider （MMD） was implemented in 0.18μm CMOS process, which had a division range from 4 to 8192, and an operating frequency range from 0. 8 GHz to 2, 7 GHz, with a current consumption of 1.25 mA.