基于FPGA的多项式基下二进制域ECC点乘设计

FPGA Design of Point multiplication of ECC with Binary Field in Polynomial Basis

文中基于经典蒙哥马利点乘算法,通过算法改进,模乘采用部分并行设计,在射影坐标系下实现模逆算法。通过VHDL语言进行设计描述,完成了椭圆曲线底层的模乘、模逆的模块设计,并通过一系列的状态机调用各个模块组合,最终完成点乘运算的设计。整个系统结构进行了优化处理,最终在Cyclone系列的EP2C35F484C5上,利用Quartus Ⅱ平台分析得出时钟频率为50.3MHZ,逻辑单元个数为25044个。

This paper achieves modular inversion algorithm in the projective coordinates based on scriptures Montgomery point multiplication by improvement, modular multiplication using partial parallel design. Moreover,this paper completed the design of point multiplication through description by VHDL, accomplished modular multiplication and modular inversion,and through a series of state machine calls each module combination.The whole structure of the system is optimized. The clock frequency of 50.3MHZ based Cyclone series EP2C35F484C5 and Logic unit number of 25044 is obtained by Quartus II platform.