VLSI互联线的延时优化研究

Optimization for Interconnect Delay of VLSI's

首先对互连线模型进行了分析,介绍了插入缓冲器来减小长线延时的方法,然后通过具体计算分析了缓冲器插入的位置、数量,以及尺寸对连线延迟的影响,得出了理论上最理想的优化方案,并给出了结合实际物理设计的优化方案和算法.最后,对一条长互联线的延迟进行了仿真计算,结果证明所给出的算法可有效地减小延时.

In this paper, interconnect delay mode is analyzed and the method of buffer insertion to reduce the long wire delay is introduced. After the impact of position, amount and size of the buffer is analyzed, the best way to reduce the interconnect delay on theory and the best way on reality are gained. At last, through simulate and calculate of a long wire delay, the algorithm is proved to be effective in reducing the delay.