基于行的实时、二维提升整数小波变换VLSI结构

A line-based,real-time VLSI architecture for 2D lifting integer-to-integer wavelet transform

提出一种基于行的实时、二维提升整数小波变换的VLSI结构。该结构包括行变换器、列变换器、中间缓存器以及输出控制单元。利用中间缓存器暂存行变换的中间结果,由输出控制单元按优先级从高到低的顺序依次输出各级小波系数。由于在硬件实现中采用基于行的提升变换结构,从而水平和垂直方向上的变换能并行处理。与现有结构相比,该结构具有并行度高、存储量低的特点,并且能够在一幅图像逐行扫描的时间间隔内完成整幅图像的多级小波变换。

A VLSI architecture that performs real-time line-based integer-to-integer discrete wavelet transform （DWT） using a lifting scheme is proposed. The architecture consists of row processors, column processors, an intermediate buffer and a control module. The intermediate buffer which is composed of FIFOs stores temporary results of horizontal filters. The control module schedules the output of wavelet coefficients to external memory with the priority from the high to low. Due to the line-based architecture in hardware implementation, both horizontal transform and vertical transform can be executed in a parallel way. Compared with other existing architectures, our architecture not only has advantages of high parallelism and reduction in storage, but also can finish multiple levels of DWT within the time that an image is scanned line by line.