基于模拟自校准技术的12位高速DAC

A 12-bit high-speed DAC based on self-calibration technique

介绍了用以改善数字模拟转换器线性特性的模拟自校准技术,分析其相对于动态器件匹配的优点,并应用于一个高速数模转换器的设计之中,在Infineon 0.25μm CMOS工艺下,4-bitDAC,工作电压1.8V,工作频率400MHz,其SNDR达到76dB(精度超过12bit),相比未采用自校准技术时的60dB提高了将近3bit,无杂散动态范围达到84.66dB,毛刺能量小于3fA-s。

In this paper,an analog self-calibration technique is introduced to improve the linearity of DAC （Digital-to-Analog Converter）,and is compared with DEM （Dynamic Element Matching）. Such self-calibration technique is implemented also in a high-speed design using the Infineon 0.25μm CMOS process. In the 4-bit DAC design,with the supply voltage of 1.8V,at the sampling frequency of 400MHz. SNDR （Signal to Noise and Distortion Ration） achieves 76dB,over 12 bits in ENOB （Effective Number of Bits）,which is 3bit higher than that without calibration technique,SFDR （Spurious Free Dynamic Range） reaches 84.66dB,and Glitch Energy is lower than 3fA-s.