基于Verilog HDL的简易数字频率计设计

Design of Simple Digital Frequency Meter Based on Verilog HDL

利用"自顶向下"的设计方法,采用Verilog HDL硬件描述语言和原理图描述相结合的方式,设计了简易数字频率计系统,并在QuartusⅡ软件环境下对设计项目进行了编译和时序仿真。仿真结果表明,该设计能根据输入信号频率进行量程自转换调整。给出了测量结果并在实验板上4位七段数码管上进行正确显示.

One designs a simple digital frequency meter system by taking advantage of the ＂top-down＂ design approach, and using the combination of Verilog HDL hardware description language and schematic description. Then, one compiles and simulates the proposed project under the software environment in the Quartus II. The simulation results show that the above mentioned design can finish automatic conversion adjustment according to the input signal frequency. The measurement results can be correctly displayed on the sevensegment digital tube in the experimental board.