密码协处理器指令级并行编译研究

Research on cipher coprocessor instruction level parallelism compiler

立足于处理器体系结构的研究,结合可重构设计技术以确保密码处理的灵活性是密码协处理器研究的重要方法,其中如何提升密码协处理器的性能是至关重要的问题。基于VLIW体系结构以及可重构设计技术,设计专用指令密码协处理器。编译器作为密码协处理器的重要组成部分,重点研究了密码协处理器指令级并行编译技术,通过提高指令级并行度来提升密码协处理器的性能。

An important method of studying cipher coprocessor is researching on processor system architecture, in combination with reconfigurable design technique to ensure flexibility of password handling.It is key to resolve improving performance of cipher coprocessor.Based on very long instruction word（VLIW）structure and reconfigurable design technique,designed specific instruction cipher coprocessor.The compiler is cipher coprocessor’s important part.This paper studied the cipher coprocessor instruction level parallelism compilation technique.Also put forward a method of enhancing the cipher coprocessor performance by increasing the instruction level parallelism.