12位单斜式线性放电ADC芯片设计

ASIC Design of a 12bit Single-Slope Wilkinson ADC

随着新型探测器的不断发展,对读出电子学的密集度和集成度要求越来越高。论文以传统线性放电ADC为基础,针对多通道读出芯片的高集成度要求,完成了12bit线性放电ADC模拟部分的ASIC设计,同时通过片外FPGA对其进行控制,兼顾测量和调试上的需求。

With the development of novel detectors, the requirement for the density and integration of readout electronics is getting more and more critical. In the paper, a design of the analog part of a 12bit Wilkinson ADC based on traditional types is completed, with the consideration of the high density in multi-channel readout chips. The chip will be controlled by external FPGA, with the requirement of measurement and debugging.