基于门控时钟技术的IC低功耗设计

Application of Gating Clock Technology in IC Design

随着数字集成电路(IC)设计的规模不断增加,降低功耗变得愈加重要。通过对门控时钟技术实现方法的分析,介绍了门控时钟技术降低功耗的有效性。通过应用实例,对逻辑设计门控和存储器门控的具体实现方法进行了详细分析,证明了门控时钟技术能够在不增加物理设计复杂度的前提下,有效降低功耗。同时门控时钟技术还可以改善时序和芯片面积,对现有设计流程不会造成任何影响。

As the digital IC design scale is increasing,lower power becomes increasingly important.By analyzing the realization method of clock gating,we describe the effectiveness of this technology to reduce power consumption,and analyze in detail the realization of the logic-gated clock and register-gated clock with examples.It is proved that gated clock can reduce power consumption without increasing the layout design complexity or affecting the existing workflow.At the same time the technology could also improve timing and chip area.