一种用于流水线ADC采样保持电路的设计

Design of Sample-Hold Circuit for a Pipelined ADC

介绍一种用于流水线ADC的采样保持电路。该电路选取电容翻转式电路结构,不仅提高整体的转换速度,而且减少因电容匹配引起的失真误差;同时使用栅压自举采样开关,有效地减少了时钟馈通和电荷注入效应;采用全差分运算放大器能有效的抑制噪声并提高整体的线性度。该采样保持电路的设计是在0.5μm CMOS工艺下实现,电源电压为5 V,采样频率为10 MHz,输入信号频率为1 MHz时,输出信号无杂散动态范围(SFDR)为73.4 dB,功耗约为20 mW。

It introduces a sampling-hold circuit of pipeline used for ADC.The pipelined ADC selects the flip-style capacitor circuit structure,it not only improves the overall conversion speed and reduces the distortion caused by capacitance matching errors while using the gate-voltage bootstrapped sampling switch,and effectively reducing the clock feedthrough and charge injection effect.A fully-difference Operational Amplifier can effectively suppress noise and improve the overall linearity.The sample-hold circuit is designed to be achieved based on 0.5 μm CMOS technology.The data in the design had been set up such as power supply voltage of 5 V,the sampling frequency of 10 MHz,the signal frequency of 1 MHz,the output signal spurious-free dynamic range（SFDR） of 73.4 dB.Power consumption is about 20 mW.